This invention relates generally to the field of semiconductors; and, in particular, to a method for yield and failure analysis in the manufacturing of semiconductors.
The process of fabricating an integrated circuit includes material preparation, circuit fabrication, wafer-probe testing, assembly, final testing and shipment. Initially a silicon ingot is cut to create individual wafers. This group of wafers are commonly referred to as a xe2x80x98lot,xe2x80x99 whereby each wafer is referred to by lot number, wafer number, resistivity, etc. Circuit fabrication may include several subsequent steps of diffusion, ion implantation, photolithography and plasma etch. The typical process step comprises the steps of deposition and growth of a thin film on the surface of the wafer, transferring the circuit pattern to a masking layer on the film, removing areas of the film not protected by the masking layer and doping exposed areas of the wafer. These steps may be repeated depending upon the process whether bipolar, MOS, CMOS or BiCMOS. Each one of these processes can produce a failure. Thus, once each individual circuit or die is complete, the purpose of wafer-probe testing, is to minimize packaging costs, and to gain information regarding process yields and final product performances.
Specifically, each die containing the completed devices and circuits are tested for basic operation, suitability for packaging, function and parametric performance. After testing, bad die are either physically marked or their locations recorded in an electronic data file. The good die are used to assemble the final device.
Although the level of automation differs from system to system, almost all wafer-probe systems are programmable. Test data is typically transmitted to a master computer database. The key components of a typical wafer-probe system include a microprocessor based controller, a tester module or subsystem, a probe card and a prober. One or more microprocessors control the tester module and prober as well as serve to provide data collection, storage and transmission. The tester module generates the input voltages, currents, and waveforms required to test the device. The tester module also measures voltages, currents and waveforms output from the device. The prober is the system component that actually handles the wafers. The prober moves the wafers in the x and y directions to align bonding pads of each die with the probe pin tips. It then raises the wafer to make contact with the probe tips and lowers the wafer after testing each die. The probe card is the printed circuit board or other assembly that holds the actual probe tips. The interface extending between the testing module and the probe include an interface board. The interface extending between the testing module and the prober is a cable interface.
The actual testing of the devices is software-driven in a sequence including continuity testing, functional testing, and parametric testing. Continuity testing is a very basic test to check whether a device turns on, if it is shorted, or if it has other fundamental flaws. Functional testing is a little more complicated than the continuity test. It tests whether the device works as a functional block. Parametric testing is the final and most complex test of the device this test checks for device performance within the given specifications. The data is stored in a management information system within the microprocessor based controller. The results of the tests and the selected sorting algorithm determine which bin the die is categorized by. The bin data is represented in a wafermap.
Finally, bad die are commonly marked by an ink dot. Inking may also be used to indicate other sorting data. The trend toward centralized data collection and storage includes computer mapping of die status. Individual die and wafer data can be averaged together to give information about the entire wafer fabrication process.
When analyzing the cause for failure of a die, the processes used to create the wafer and the equipment used to test each die must be taken into consideration. In manufacturing semiconductor wafers, thousands of wafer lots may be examined by a single piece of equipment. It is therefore essential that if a single piece of equipment is causing wafers to fail that it be repaired.
Processes such as photolithography, ion implantation, and plasma etch use specific equipment to complete the desired process. Several factors contribute to recognizing the exact failing process. The need to identify this process is crucial to manufacturing, quality control, and processing of subsequent wafers. There, however, exist no system available that identifies each and every aforementioned process wherein a fault lies, nor pinpoints the associated malfunctioning equipment. Thus, there exists a need for a system that identifies which process is causing the wafer to fail and determines the associated equipment. The need for identifying this process is crucial to manufacturing, quality control, and processing of subsequent wafers.
An automated wafer yield and failure analysis system identifies the particular semiconductor manufacturing process which cause wafer defective data is provided. The yield and failure analysis systems further identifies each and every aforementioned process wherein a fault lies and pinpoints the associated malfunctioning equipment. The given process is crucial to manufacturing, quality control, and processing of subsequent wafers.
The apparatus includes wafer inspection instrumentation whereby each wafer within a given lot is probed and a series of tests are applied. A data collection means, such as a computer having a central database system, collects wafer defect data from the wafer inspection instrument. The wafer defect data is in the form of x, y and z coordinates. This data is stored in a first relational database of the central database system. Accordingly, the first relational database compiles a composite wafermap for each lot. A conversion means such as software associated with the wafer inspection instrument applies Fast Fourier Transform equations to collected wafer defect data and converts this data into FFT signature data.
The converted wafer defect data is stored in a second relational database in the central database system wherein the stored converted wafer defect data patterns are retrievable based on selected criteria. Software may be used to compare the present wafer defect data with the stored converted wafer defect data patterns to generate correlation coefficients. Only if the correlation coefficients are within predetermined range, the converted wafer defect data pattern is stored in this second relational database. At least one user interface workstation displays data from both databases, allowing the user to select converted wafer defect data and analyzed data in real time.
In particular, the invention provides an apparatus and method of identifying the process associated with the die failure and, in particular, the invention provides a method of identifying a specific bin, piece of equipment, or even maintenance procedure. It includes probing the wafer to gain information regarding process yields and final product performances. Automating yield and failure analysis requires precision in order to account for all the information. Thus, the invention utilizes statistical and mathematical models to gather and examine the data. Data is compiled and updated for each wafer in a given lot to form a composite wafermap. This data is stored in a first database and accessible for continuous improvement of the yield and failure analysis apparatus.
Analyzing composite wafermaps is a very efficient and accurate method for recognizing failures on semiconductor wafers. By viewing these pass/fail patterns for numerous lots, the major problem can be easily identified, instead of having to step through each wafer. Accordingly, by providing the ability to view hundreds of lots and thousands of wafers on a single screen, the invention reduces the time needed to identify an error significantly. Thus, a broad range of applications as well as a wide array of analysis may be covered.
More particularly, according to the aforementioned embodiment of the present invention, the Fast Fourier Transform (FFT) of the signal generated from the wafer probe analysis yields a signature which serves to identify the type of wafer error that exists. The second relational database in a management information system within the computer is generated which includes all possible FFT patterns encountered during the manufacturing and testing of a wafer. By using a pattern recognition algorithm, specific process errors are recognized. A number of variables need are considered when determining the exact failing process.
The FFT signature is analyzed to determine the type of defect that exists. Comparison occurs between the FFT signature and those in the second relational database of patterns where previous wafermap patterns of electrical bin data is stored. In order to compare these patterns, the invention uses the FFT signature in matrix format and then generates a correlation coefficient for the given wafermap with each pattern. Through the use of a statistical tool that gives a numerical value of how close the match is between the patterns, the correlation coefficients are derived. Those patterns that meet a pre-defined criteria are stored in a third relational database.
Using the correlation coefficients, wafermaps are arranged in descending order such that, the highest correlation coefficient is listed first with its corresponding pattern. The invention automatically generates a pareto chart of the correlation coefficients, saving the user the trouble of identify the failing pattern that the wafermap corresponds to best.
An exceptions report indicates the necessary information to identify the exact problem. It includes the total number of defects encountered, which type of error is most significant, and the value of the correlation coefficient. The exceptions report can be prepared in a variety of different ways including sorting by yield, tracking over processes, overlay of maps, tracking over any range of time, viewing by volume of distribution, and composite maps for either a single key or numerous keys. Data is presented in an easy analyzable form, available for all the processes associated with the manufacturing of the semiconductor.
According to another embodiment of the failure and yield analysis management system, continuous improvement of the failure and yield analysis database is established. A first query of the first relational database is executed to generate a sub-database based upon user selection criteria. The user has the ability to zoom in and out on bin data, vary the statistical sensitivity, alter the segregation singularity, and generate pareto charts. From the resulting analysis, the system determines whether the new pattern generated should be included within the Patterns Database for future reference during in-line process testing, increasing failure and yield system reliability.